Our high performance netlist based PCB design package perfectly complements our powerful ISIS schematic capture software and features both automatic component placement and a highly effective Rip-Up and Retry auto-router.
ISIS and ARES together form a complete Proteus PCB Design package.
ARES PCB Layout Includes:
Design Automation:
"PCB Design is our business. We review PCB Layout software on an ongoing basis and Labcenter has topped the list for the last 10 years. Certainly the most productive and very,very affordable. We have licences for other very expensive products but they don't get much use.."
All Proteus PCB Design solutions include both the ISIS Schematic Capture package and the ARES PCB layout package. Cost is dependant on both the required design capacity and the required feature set.
An overview of available solutions can be found here, whilst the associated pricelist is here. Feel free to contact us should you wish more information or to further discuss requirements.
ARES features a state of the art layout database capable of representing the most complex of PCB designs. Placement resolution is 10 nanometers within a maximum board size of 20m. Components and other objects may be rotated in 0.1 degree increments whilst padstacks facilitate the achievement of maximum routing area on inner layers.
During the placement phase, ARES displays both the ratsnest and force vectors. Both are updated in real time when you drag components. The ratsnest is also automatically updated during routing - add a track and a ratsnest line with disappear; delete a track and one will re-appear. You can also configure ratsnest colours and visibility on a per strategy basis for clarity - for example assigning power lines in blue and signal lines in green.
The system fully supports design modifications - if you change the schematic and re-load the netslist, ARES will flag up exactly which components and/or tracks are affected. Equally, pin-swaps and gate-swaps made in ARES are automatically fed back to the schematic.
Manual routing makes no requirement that you start from the ratsnest lines (rubberbanding). You can place tracking in any way you wish and ARES will remove ratsnest lines as the connections are actually completed.
When editing routes you can re-route or delete any section of a track, irrespective of how it was originally placed. Commands are also provided to change the thickness and/or layer of any section of tracking.
Track operations
Track selection configuration
If thick tracks are laid between obstacles such as IC pads, ARES will automatically 'neck' in order to maintain the current design rules.
Curved tracks can be laid down simply by pressing the CTRL key and marking the route with the mouse.
Tracks can be easily edited and repositioned as required.
ARES features the ultimate in power plane support - user placeable polygonal regions within which inner boundaries are automatically created around existing pads and tracking. Change the pads and tracking and the boundaries are recomputed to maintain design rule clearances. Thermal reliefs are supported and you can choose whether to hatch or fill each polygon. All computation is based on grid-less shape geometry and occurs in the background so that there is no interference in manual board placement for computationally intensive layouts.
Close up of two ARES zones with the same board. The top-left shows a hatched zone with thermally relieved connections whilst the lower-right shows a solid zone with solid, unrelieved, connections.
Live DRC reporting on the status bar.
During manual routing, ARES checks each track as you place it and warns you if any design rules (physical/electrical) are broken. You can also run global physical and electrical design rule checks at any time. The latter produces a report listing any missing or extra connections - double click on any entry in the list, and ARES will zoom in to show you exactly where the error is located on the PCB.
The supplied libraries cover a large range of through hole components including all the most common IC, transistor, diode and connector packaging types. We also supply as standard the full IEC libraries and SMT footprints which include all the standard discrete and IC packaging styles. New packages can easily be created directly on the drawing whilst ARES also supports general 2D drafting features.
As well as supporting the basic ability to output your PCB to standard windows printers, ARES provides an optimized HPGL driver for pen plotters, and a full set of features for professional board manufacturing.
Gerber is supported in both the RS274D and the newer RS274X formats whilst a standard excellon format file is produced for drilling machines. In addition, an ASCII file listing component positions and orientations is produced for use with Pick and Place machinery.
A gerber viewer is also provided, allowing you to check that Gerber files contain the expected data, and to panelise boards prior to issuing them for manufacture.
The 3D Visualisation Tool (3D Viewer) in ARES provides a way to extrude a layout and view the board as it would appear in real life. This is extremely useful as a design aid during board layout.
3D Visualisation of the Microchip Technologies PICDEM2+ Virtual Evaluation Board.
Specifying 3D model parameters in the Make Package dialogue form inside the ARES Application.
Navigation, both orbital and 'fly by' is extremely intuitive and mouse controlled. ARES libraries come supplied with 3D footprints and comprehensive support for creating custom 3D footprints directly inside ARES or by importing models via the standard *.3ds file format.
Automatic component placement makes it possible to design an entire board with absolute minimum of effort on your part. Alternatively, since the placer can operate interactively, you can pre-place critical components first and then let ARES auto-place the rest.
Our grid based router is both flexible and fast and can route using any track thickness or via width, at 90 or 45 degrees, and on 1-8 layers. It was placed in the top Category A in the recent review of PCB software (Electronics & Wireless World magazine).
The range of routing grids available enables you to trade off routing density against execution speed with densities of 1, 2 or 3 traces between IC pads. The router also has special routines which enable it to form 'fan outs' from rows of SMT pads which would otherwise be off grid, thus enabling it to perform well with boards containing SMT parts.
The Rip-Up and Retry mode enables it to remove and replace tracks which block others giving 100% completion on most medium density boards routed at 50 or 25 thou. Meanwhile, our innovative costing/scheduling logic reduces the via count by as much as four fold over low-medium cost routers. Finally, you can run the tidy pass which reduces both track length and via count whilst improving the aesthetic quality of your board at the same time.
For customers looking for the very latest in autorouting technology we have provided an integrated bi-directional interface to the ELECTRA autorouter. This router uses adaptive shape based autorouting algorithms to achieve completion, often surpassing industry standard benchmarks. More information on ELECTRA, links to a trial download and pricing can be found here.
Routing setup with the integrated ELECTRA Configuration dialogue form
